1、英文原文OVERCURRENT RELAY ON A FPGA CHIPAbstractA new hardware approach for implementing overcurrent relays is presented in this paper. An overcurrent relay is implemented on a field programmable gate array (FPGA) chip (Xilinxs XC3020-50-PC84C). The hardware design of the overcurrent relay is based on a
2、 three-stage pipelined architectureA relationship that describes the time -current characteristics of the relay in terms of the clock frequency of the chip is developed.1. INTRODUCTIONMicroprocessors have successfully implemented protective power relays. A typical microprocessor-based relay requires
3、 more than ten general-purpose standard chips l2 3.The basic chips necessary for implementation include at least read/write memory (RWM) chip ,input port in addition to the microprocessor .The disadvantages of using several standard chips in the implementation of a protective relay can be summarized
4、 in the following points.1. These chips consume board space. 2. They require labor or Production time for assembly. 3. They decrease the reliability because of the mechanical connections.4. They consume power. Advances in Very Large Scale Integrated (VLSI)4 systems have made the design and fabricati
5、on of Application , Specific Integrated Circuits ( ASICs )5 feasible . A recently introduced type of ASIC is the field programmable gate array （FPGA) 6.FPGAs are ASICs which combine the attractive features of both programmable logic devices (PLDs)7and gate arrays 4.This paper reports on the implemen
6、tation of an overcurrent relay on a field programmable gate array (FPGA) chip, Xilinxs XC3020-50- PC84C8. Xilinxs development system 8 is used for the software and hardware development of the FPGA chip. A three-stage pipelined architecture is adopted in the realization of the relay hardware. The imp
7、lemented overcurrent relay has twos 8-bit inputs: the current being monitored and a threshold value; and two single bit inputs: reset and clock. The one-bit trip signal is the only output provided by the relay. The threshold input, which can be varied,etermines the minimum fault current .The reset i
8、nput is provided for initialization and resetting after tripping .In general ,a protective relay on ASIC such as FPGA gives the following advantges.a. Significant reduction in power consumption all board space. b. No labor or production time for assembly. c. No software programs are written and/or d
9、ebugged.d. Production cost is reduced while perfonnance and reliability are increased.The outline of this paper is as follows. Section 2 describes the three-staged pipelined architecture of the overcurrent relay. Brief description of the FPGA chip and the experimental results of the overcurrent rela
10、y are Presented in section3. Concluding remarks are given in section42. ARCHITECTURE OF OVERCURRENT RELAYThe basic function of an overcurrent relay is to monitor the current of the line being protected. Whenever the current exceeds a predetermined threshold, the relay goes through a delay routine th
11、en activates the trip signal. Figure 1 illustrates the time-current characteristics of the overcurrent relay. The basic digital circuits needed for the implementation include a counter, look-up table in the form of a combinational circuit, and two comparators. The counter measures the duration of th
12、e fault which means that the value of the counter is zero under normal conditions. The look-up table stores the time-current characteristics, shown in Figure 1, of the relay. The comparators make two decisions: The first decision is whether there is a fault or not; and the second decision is whether
13、 to activate the trip signal or not. A pipelined architecture is selected for the hardware realization of the overcurrent relay. Pipelined architectures are regular and simple to implement and at the same time they provide high throughput. Only three stages are needed for the overcurrent relay as sh
14、own in Figure 2. In the figure the stages are separated by latches that allow all three stages to operate in parallel. The execution time of each stage is less than one period of the system clock. Therefore the system clock passes the data through the system by triggering the latches simultaneously.
15、 The tasks of the three stages are outlined below.Stage l: The first stage has two circuits: the look-up table and a comparator. First, the two inputs to the stage, the current and the threshold value, are latched-in. Using the current, the time-to-trip (ttt) is read out of the look-up table. At the
16、 same time, the current and the threshold value are compared and fault condition (fc) signal is computed. The value of fc is equal to one if and only if the current exceeds the threshold value, that isFigure 1 Time-current characteristics of overcurrent relays Overcurrent relayFigure 2 -Pipelined architecture for overcurrellt relaysThe outputs ttt amd fc of the first stage are passed to the second stage.
